1. Field of the Invention
The present invention relates to a voltage generating apparatus for a semiconductor memory element using a complementary metal-oxide semiconductor (hereinafter referred to as a CMOS) circuit. More particularly, it relates to a voltage generating apparatus for performing a stable operation by varying a pumping ability in response to a frequency variation in a circuit for generating a bulk bias voltage Vbb (namely, a substrate voltage) and a high-voltage Vpp.
2. Description of the Prior Art
In general, a high voltage Vpp is used as a transistor's gate voltage in a memory cell, a voltage for isolating a cell array block, and a n-channel MOS (hereinafter referred to as NMOS)-pull-up-transistor's gate voltage in a data output buffer. The bulk bias voltage Vbb is used as a NMOS bulk electrode.
FIG. 1 is a block diagram illustrating a conventional apparatus for generating a bulk bias voltage or high voltage.
The conventional apparatus for generating a bulk bias voltage or high voltage includes:
a ring oscillator for outputting a clock signal having a predetermined period to an electric charge pumping portion when a power-supply is applied to a chip; PA1 an electric charge pumping portion which receives the clock signal from the ring oscillator as an input, and generates a bulk bias voltage Vbb or a high voltage Vpp; and PA1 a level sensing portion which senses an output voltage of the electric charge pumping portion, and determines whether the ring oscillator is operated or not. PA1 a frequency dividing circuit which reduces a frequency when the frequency of an external clock signal is too fast, and outputs the reduced frequency to an input terminal of a switch and delay portion; PA1 a frequency doubling portion which increases a frequency when a frequency of an external clock signal is too slow, and outputs the increased frequency to an input terminal of a switch and delay portion; PA1 a switch and delay portion which receives the external clock signal and an output signal of a level sensing portion, is controlled by the output signal of the level sensing portion, transmits the external clock signal to an electric charge pumping portion, cuts off or delays a transmission of the external clock signal; PA1 an electric charge pumping portion which is operated by an output signal of the switch and delay portion, and generates a high voltage or a bulk bias voltage; and PA1 a reference electric potential sensing portion which is connected between an output terminal of the electric charge pumping portion and an input terminal of the switch and delay portion, and controls the switch and delay means by sensing an electric potential of the output terminal of the electric charge pumping portion.
The conventional apparatus is operated as follows.
First, when a power-supply is applied to the chip, the ring oscillator and the electric charge pumping portion are operated, thereby making a high voltage Vpp or a bulk bias voltage Vbb with a desirable level. The level sensing portion is then operated, the voltage Vpp or Vbb is pumped by a desirable level, and therefore the level sensing portion has a predetermined level.
In this case, if the high-voltage Vpp increases over the predetermined level of the level sensing portion or is lowered below the predetermined level of the level sensing portion, the level sensing portion stops an operation of the ring oscillator or drives the ring oscillator, thereby maintaining a constant high voltage.
On the contrary, if the bulk bias voltage Vbb increases over the predetermined level of the level sensing portion or is lowered below the predetermined level of the level sensing portion, the level sensing portion stops an operation of the ring oscillator or drives the ring oscillator, thereby maintaining a constant bulk bias voltage.
However, since the conventional apparatus for generating the bulk bias voltage or high voltage uses an internal oscillator clock signal having a constant period as an operation signal of the electric charge pumping portion, a pumping ability is not automatically corresponded to a speed of a column operation.